Abhishek Bhattacharjee
A. Bartlett Giamatti professor of Computer ScienceCards
About
Research
Publications
2025
pulse: Accelerating Distributed Pointer-Traversals on Disaggregated Memory
Tang Y, Lee S, Bhattacharjee A, Khandelwal A. pulse: Accelerating Distributed Pointer-Traversals on Disaggregated Memory. 2025, 858-875. DOI: 10.1145/3669940.3707253.Peer-Reviewed Original Research
2024
Characterizing Emerging Page Replacement Policies for Memory-Intensive Applications
Wu M, Isaacman S, Bhattacharjee A. Characterizing Emerging Page Replacement Policies for Memory-Intensive Applications. 2024, 00: 284-294. DOI: 10.1109/iiswc63097.2024.00033.Peer-Reviewed Original ResearchPage replacementReplacement policyMemory-intensive workloadsMemory-intensive applicationsPage replacement policyPaging algorithmsOperating systemPage migrationWorkload executionLRU algorithmMemory technologiesSystem configurationMemory managementData movementMemory systemLRULinux kernelMemory footprintComputer systemsPerformance variationWorkloadReplacementRe-inventMemoryClockUnderstanding Address Translation Scaling Behaviours Using Hardware Performance Counters
Lindsay N, Bhattacharjee A. Understanding Address Translation Scaling Behaviours Using Hardware Performance Counters. 2024, 00: 236-246. DOI: 10.1109/iiswc63097.2024.00029.Peer-Reviewed Original ResearchTranslation lookaside bufferMemory management unitPage table walksPage tableReducing Translation Lookaside BufferMemory footprintHardware performance countersPerformance counter dataIncreasing memory footprintLookaside bufferPerformance countersAccess patternsReal machineSuperpagesCacheHit rateProgram instancesWorkloadInput generationCounter dataFootprintManagement unitsDegradation performanceMemoryWalking cycleMosaic Pages: Big TLB Reach With Small Pages
Han J, Gosakan K, Kuszmaul W, Mubarek I, Mukherjee N, Sriram K, Tagliavini G, West E, Bender M, Bhattacharjee A, Conway A, Farach-Colton M, Gandhi J, Johnson R, Kannan S, Porter D. Mosaic Pages: Big TLB Reach With Small Pages. IEEE Micro 2024, 44: 52-59. DOI: 10.1109/mm.2024.3409181.Peer-Reviewed Original ResearchDistributed Brain–Computer Interfacing With a Networked Multiaccelerator Architecture
Pothukuchi R, Sriram K, Gerasimiuk M, Ugur M, Manohar R, Khandelwal A, Bhattacharjee A. Distributed Brain–Computer Interfacing With a Networked Multiaccelerator Architecture. IEEE Micro 2024, 44: 106-115. DOI: 10.1109/mm.2024.3411881.Peer-Reviewed Original Research
2023
CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators
Alam F, Lee H, Bhattacharjee A, Awad A. CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators. 2023, 32-48. DOI: 10.1145/3613424.3614311.Peer-Reviewed Original ResearchMemory management unitSecure access controlThird-party intellectual propertyGeneral-purpose processorsCryptography-based approachesCustom acceleratorsEdge devicesHardware acceleratorsAccess controlIntellectual propertySoftware changesArt solutionsGood scalabilityMemory accessCloud systemsData centersData structureChip acceleratorsDesign timeO devicesReconfigurable logicSystem integratorsSignificant performanceSystem throughputEvaluation results
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