Abhishek Bhattacharjee
A. Bartlett Giamatti professor of Computer ScienceCards
About
Research
Publications
2025
Scalable Far Memory: Balancing Faults and Evictions
Pan Y, Lala Y, Unal M, Ren Y, Lee S, Bhattacharjee A, Khandelwal A, Kashyap S. Scalable Far Memory: Balancing Faults and Evictions. 2025, 136-152. DOI: 10.1145/3731569.3764842.Peer-Reviewed Original ResearchThread countEviction operationsData-intensive applicationsMulti-core machinesBatch processing applicationsMemcached applicationSynchronization overheadsPipelined executionScalability bottlenecksMemory supportMemory systemMemory allocationLibrary OSApplication codeLinux kernelScalability challengesPercentile latencyScalabilityDesign principlesEvictionThreadsMemory capacityPage accountMachineTLBPaging and the Address-Translation Problem
Bender M, Bhattacharjee A, Conway A, Farach-Colton M, Johnson R, Kannan S, Kuszmaul W, Mukherjee N, Porter D, Tagliavini G, Vorobyeva J, West E. Paging and the Address-Translation Problem. ACM Transactions On Algorithms 2025, 21: 1-22. DOI: 10.1145/3737700.Peer-Reviewed Original ResearchDataflow-Specific Algorithms for Resource-Constrained Scheduling and Memory Design
Bhattacharjee A, Liu Q, Manohar R, Pothukuchi R, Ugur M. Dataflow-Specific Algorithms for Resource-Constrained Scheduling and Memory Design. 2025, 101-115. DOI: 10.1145/3694906.3743342.Peer-Reviewed Original ResearchRed-blue pebble gameMemory designOn-chip memory designResource-constrained schedulingMemory area reductionStatic power reductionDataflow specificationSlow memoryData movementFast memoryPower constraintsPower reductionComputational kernelsPebble gameOperation scheduleResource-constrained computing environmentOptimal scheduleResource-constrained systemsArea reductionOperating costsConstrained operationModular compositionSchedulingImplantable devicesComputing environmentForesee: A Modular and Open Framework to Explore Integrated Processing on Brain-Computer Interfaces
Yadav A, Garcia F, Gonzalez A, Trevisan B, Xu A, Ugur M, Bhattacharjee A, Pothukuchi R. Foresee: A Modular and Open Framework to Explore Integrated Processing on Brain-Computer Interfaces. Annual International Conference Of The IEEE Engineering In Medicine And Biology Society (EMBC) 2025, 00: 1-7. PMID: 41337318, DOI: 10.1109/embc58623.2025.11254710.Peer-Reviewed Original ResearchConceptsBrain-computer interfaceOn-device processingOn-deviceSeizure detection methodTarget hardware platformDesign space exploration frameworkHardware platformComputational neuroscientistsSignal processing functionsReal hardwareBrain-computerExploration frameworkAd hocProcessing functionsDetection methodProcessorModular interfaceAlgorithmProcessor designPerformance needsFrameworkInterfaceHardwareModularityLibrarySingle-Address-Space FaaS with Jord
Li Y, Bhattacharyya A, Kumar M, Bhattacharjee A, Etsion Y, Falsafi B, Kashyap S, Payer M. Single-Address-Space FaaS with Jord. 2025, 694-707. DOI: 10.1145/3695053.3731108.Peer-Reviewed Original ResearchService-level objectivesMemory isolationFunction-as-a-ServiceState-of-the-art systemsState-of-the-artFAAS systemCloud paradigmSoftware developmentMicroservice workloadsFunction dispatchFunctional semanticsPerformance bottleneckExecution timeVirtual memoryCross-functional communicationMicroservicesCo-designExecutionColocating functionsFaaS.MicroVMsOverheadsServerSemanticsThroughputpulse: Accelerating Distributed Pointer-Traversals on Disaggregated Memory
Tang Y, Lee S, Bhattacharjee A, Khandelwal A. pulse: Accelerating Distributed Pointer-Traversals on Disaggregated Memory. 2025, 858-875. DOI: 10.1145/3669940.3707253.Peer-Reviewed Original Research
2024
Characterizing Emerging Page Replacement Policies for Memory-Intensive Applications
Wu M, Isaacman S, Bhattacharjee A. Characterizing Emerging Page Replacement Policies for Memory-Intensive Applications. 2024, 00: 284-294. DOI: 10.1109/iiswc63097.2024.00033.Peer-Reviewed Original ResearchPage replacementReplacement policyMemory-intensive workloadsMemory-intensive applicationsPage replacement policyPaging algorithmsOperating systemPage migrationWorkload executionLRU algorithmMemory technologiesSystem configurationMemory managementData movementMemory systemLRULinux kernelMemory footprintComputer systemsPerformance variationWorkloadReplacementRe-inventMemoryClockUnderstanding Address Translation Scaling Behaviours Using Hardware Performance Counters
Lindsay N, Bhattacharjee A. Understanding Address Translation Scaling Behaviours Using Hardware Performance Counters. 2024, 00: 236-246. DOI: 10.1109/iiswc63097.2024.00029.Peer-Reviewed Original ResearchTranslation lookaside bufferMemory management unitPage table walksPage tableReducing Translation Lookaside BufferMemory footprintHardware performance countersPerformance counter dataIncreasing memory footprintLookaside bufferPerformance countersAccess patternsReal machineSuperpagesCacheHit rateProgram instancesWorkloadInput generationCounter dataFootprintManagement unitsDegradation performanceMemoryWalking cycleMosaic Pages: Big TLB Reach With Small Pages
Han J, Gosakan K, Kuszmaul W, Mubarek I, Mukherjee N, Sriram K, Tagliavini G, West E, Bender M, Bhattacharjee A, Conway A, Farach-Colton M, Gandhi J, Johnson R, Kannan S, Porter D. Mosaic Pages: Big TLB Reach With Small Pages. IEEE Micro 2024, 44: 52-59. DOI: 10.1109/mm.2024.3409181.Peer-Reviewed Original ResearchDistributed Brain–Computer Interfacing With a Networked Multiaccelerator Architecture
Pothukuchi R, Sriram K, Gerasimiuk M, Ugur M, Manohar R, Khandelwal A, Bhattacharjee A. Distributed Brain–Computer Interfacing With a Networked Multiaccelerator Architecture. IEEE Micro 2024, 44: 106-115. DOI: 10.1109/mm.2024.3411881.Peer-Reviewed Original Research
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