Rajit Manohar
John C. Malone Professor of Electrical EngineeringCards
About
Research
Publications
2025
A deterministic neuromorphic architecture with scalable time synchronization
Li C, Imam N, Manohar R. A deterministic neuromorphic architecture with scalable time synchronization. Nature Communications 2025, 16: 10329. PMID: 41285861, PMCID: PMC12645053, DOI: 10.1038/s41467-025-65268-z.Peer-Reviewed Original ResearchDataflow-Specific Algorithms for Resource-Constrained Scheduling and Memory Design
Bhattacharjee A, Liu Q, Manohar R, Pothukuchi R, Ugur M. Dataflow-Specific Algorithms for Resource-Constrained Scheduling and Memory Design. 2025, 101-115. DOI: 10.1145/3694906.3743342.Peer-Reviewed Original ResearchRed-blue pebble gameMemory designOn-chip memory designResource-constrained schedulingMemory area reductionStatic power reductionDataflow specificationSlow memoryData movementFast memoryPower constraintsPower reductionComputational kernelsPebble gameOperation scheduleResource-constrained computing environmentOptimal scheduleResource-constrained systemsArea reductionOperating costsConstrained operationModular compositionSchedulingImplantable devicesComputing environmentPipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis
Li R, Berkley L, Manohar R. PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis. 2025, 1-7. DOI: 10.1109/dac63849.2025.11133111.Peer-Reviewed Original ResearchMaelstrom: A Logic Synthesis Technique for Asynchronous Circuits
Srinivasan K, Manohar R. Maelstrom: A Logic Synthesis Technique for Asynchronous Circuits. IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems 2025, PP: 1-1. DOI: 10.1109/tcad.2025.3572364.Peer-Reviewed Original ResearchAutomated Decomposition of Concurrent Programs for Asynchronous Logic Synthesis
Srinivasan K, Manohar R. Automated Decomposition of Concurrent Programs for Asynchronous Logic Synthesis. 2025, 00: 99-107. DOI: 10.1109/async65240.2025.00022.Peer-Reviewed Original ResearchAsynchronous, event-driven readout for large-scale imaging devices
Purohit P, Manohar R. Asynchronous, event-driven readout for large-scale imaging devices. 2025, 00: 118-125. DOI: 10.1109/async65240.2025.00024.Peer-Reviewed Original ResearchTranslating General Slack Elastic Programs into Dataflow Circuits
Wen X, Li R, Manohar R. Translating General Slack Elastic Programs into Dataflow Circuits. 2025, 00: 80-88. DOI: 10.1109/async65240.2025.00020.Peer-Reviewed Original ResearchPipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis
Li R, Manohar R. PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis. 2025, 182-182. DOI: 10.1145/3706628.3708842.Peer-Reviewed Original ResearchThe neurobench framework for benchmarking neuromorphic computing algorithms and systems
Yik J, Van den Berghe K, den Blanken D, Bouhadjar Y, Fabre M, Hueber P, Ke W, Khoei M, Kleyko D, Pacik-Nelson N, Pierro A, Stratmann P, Sun P, Tang G, Wang S, Zhou B, Ahmed S, Vathakkattil Joseph G, Leto B, Micheli A, Mishra A, Lenz G, Sun T, Ahmed Z, Akl M, Anderson B, Andreou A, Bartolozzi C, Basu A, Bogdan P, Bohte S, Buckley S, Cauwenberghs G, Chicca E, Corradi F, de Croon G, Danielescu A, Daram A, Davies M, Demirag Y, Eshraghian J, Fischer T, Forest J, Fra V, Furber S, Furlong P, Gilpin W, Gilra A, Gonzalez H, Indiveri G, Joshi S, Karia V, Khacef L, Knight J, Kriener L, Kubendran R, Kudithipudi D, Liu S, Liu Y, Ma H, Manohar R, Margarit-Taulé J, Mayr C, Michmizos K, Muir D, Neftci E, Nowotny T, Ottati F, Ozcelikkale A, Panda P, Park J, Payvand M, Pehle C, Petrovici M, Posch C, Renner A, Sandamirskaya Y, Schaefer C, van Schaik A, Schemmel J, Schmidgall S, Schuman C, Seo J, Sheik S, Shrestha S, Sifalakis M, Sironi A, Stewart K, Stewart M, Stewart T, Timcheck J, Tömen N, Urgese G, Verhelst M, Vineyard C, Vogginger B, Yousefzadeh A, Zohora F, Frenkel C, Reddi V. The neurobench framework for benchmarking neuromorphic computing algorithms and systems. Nature Communications 2025, 16: 1545. PMID: 39934126, PMCID: PMC11814226, DOI: 10.1038/s41467-025-56739-4.Peer-Reviewed Original ResearchNeuromorphic computing algorithmsNeuromorphic research fieldNeuromorphic algorithmsNeuromorphic approachHardware-independentAI applicationsCommunity of researchersProject websiteComputational algorithmResearch directionsReference frameworkAlgorithmResearch fieldProject updateBenchmark measuresSystematic methodologyFrameworkConventional methodsTechnological advancesBenchmarks
2024
Mixed-Level Emulation of Asynchronous Circuits on Synchronous FPGAs
Dashkin R, Manohar R. Mixed-Level Emulation of Asynchronous Circuits on Synchronous FPGAs. IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems 2024, 44: 1516-1528. DOI: 10.1109/tcad.2024.3479077.Peer-Reviewed Original Research